Along with demands for microfabrication, high integration, and high speed of a semiconductor device, it is required to reduce a wiring resistance, reduce an inter-wiring capacitance, and improve reliability of a wiring. For the reduction of the wiring resistance, a copper (Cu) wiring having a lower resistance than that of a conventional aluminum (Al) alloy is used.
For the reduction of the inter-wiring capacitance, instead of conventional silicon oxide (SiO2), an insulating film having a lower dielectric constant than that of the silicon oxide (hereinafter, which is referred to as a low dielectric constant film) is used as an interlayer insulating film of the wiring.
Japanese Patent Application Laid-Open Publication No. 2004-158832 (Patent Document 1) discloses a technique related to a multilayered wiring using a SiOC film as the low dielectric constant film for the interlayer insulating film.
Meanwhile, in a viewpoint of ensuring reliability of connection between a plug and a wiring, the following techniques are disclosed.
Japanese Patent Application Laid-Open Publication No. 2006-339623 (Patent Document 2) discloses a technique for preventing occurrence of voids upon forming a metal layer 104 by selectively etching an interlayer insulating film 102 so that a surface of the uppermost portion of a contact plug 103 in the lowermost layer is lower than a surface of the uppermost portion of the interlayer insulating film 102, and then, forming the metal layer 104 on the interlayer insulating film 102.
Also, Japanese Patent Application Laid-Open Publication No. 2006-73635 (Patent Document 3) discloses a technique for forming a small upper portion of a contact 7 by processing a conductive material deposited on an interlayer insulating film 6.